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1/31 TDA7580 july 2002 this is preliminary information on a new product now in development. details are subject to change without notice. n fm/am if sampling dsp n on-chip analogue to digital converter for 10.7mhz if signal conversion n software based channel equalization n fm adjacent channel suppression n reception enhancement in multipath condition n stereo decoder and weak signal processing n 2 channels serial audio interface (sai) with sample rate converter n i 2 c and buffer-spi control interfaces n rds filter, demodulator & decoder n inter processor transport interface for antenna and tuner diversity n front-end agc feedback description the TDA7580 is an integrated circuit implementing an advanced mixed analogue and digital solution to perform the signal processing of a am/fm channel. the hw&sw architecture has been devised so to have a digital equalization of the fm/am channel; hence a real rejection of adjacent channels and any other signals interfering with the listening of the de- sired station. in severe multiple paths conditions, the reception is improved to get the audio with high qual- ity. tqfp64 ordering number: TDA7580 product preview fm/am digital if sampling processor block diagram a/d sai1 sai0 src i2c/spi dac cgu oscillator i2c/spi hs3i rds if digital signal processor
TDA7580 2/31 description (continued) the algorithm is self-adaptive, thus it requires no on-the-field adjustments after the parameters optimization. the chip embeds a band pass sigma delta analogue to digital converter for 10.7mhz if conversion from a tuner device (it is highly recommended the tda7515). the internal 24bit-dsp allows some flexibility in the algorithm implementation, thus giving some freedom for customer required features. the total processing power offers a significant headroom for customers software requirement, even when the channel equalization and the decoding software is running. the program and data memory space can be loaded from an external non volatile memory via i 2 c or spi. the oscillator module works with an external 74.1mhz quartz crystal. it has very low electro magnetic interfer- ence, as it introduces very low distortion, and in any case any harmonics fall outside the radio bandwidth. the companion tuner device receives the reference clock through a differential ended interface, which works off the oscillator module by properly dividing down the master clock frequency. that allows the overall system saving an additional crystal for the tuner. after the if conversion, the digitized baseband signal passes through the base band processing section, either fm or am, depending on the listener selection. the fm base band processing comprises of stereo decoder, spike detection and noise blanking. the am noise blanking is fully software implemented. the internal rds filter, demodulator and decoder features complete functions to have the output data available through either i 2 c or spi interface. no dsp support is needed but at start-up, so that rds can work in back- ground and in parallel with other dsp processing. this mode (rds-only) allows current consumption saving for low power application modes. an i 2 c/spi interface is available for any control and communication with the main micro, as well as rds data interface. the dsp spi block embeds a 10 words fifo for both transmit and receive channels, to lighten the dsp task and frequently respond to the interrupt from the control interface. serial audio interface (sai) is the ideal solution for the audio data transfer, both transmit and receive: either master or slave. the flexibility of this module gives a wide choice of different protocols, including i 2 s. two fully independent bidirectional data channels, with separate clocks allows the use of TDA7580 as general purpose digital audio processor. a fully asynchronous sample rate converter (asrc) is available as a peripheral prior to sending audio data out via the sai, so that internal audio sampling rate (~36khz and fm/am mode) can be adapted by upconver- sion to any external rate. an inter processor transport interface (hs 3 i, high speed synchronous serial interface) is also available for a modular system which implements dual tuner diversity , thus enhancing the overall system performance. it is about a synchronous serial interface which exchanges data up to the mpx rate. it has been designed to reduce the electro magnetic interference toward the sensitive analogue signal from the tuner. general purpose i/o registers are connected to and controlled by the dsp, by means of memory map. a debug and test interface is available for on-chip software debug as well as for internal registers read/write operation.
3/31 TDA7580 absolute maximum ratings warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed a t these extremes. note: 1. v dd3 refers to all of the nominal 3.3v power supplies (v ddh , v osc , v ddsd ). v dd refers to all of the nominal 1.8v power supplies (v dd , v mtr ). 2. during normal mode operation vdd3 is always available as specified 3. during fail-safe mode operation vdd3 may be not available. thermal data symbol parameter value unit vdd vdd3 power supplies (1) nom. 1.8v nom. 3.3v -0.5 to 2.5 -0.5 to 4.0 v v analog input or output voltage belonging to 3.3v io ring (v ddsd , v ddosc ) -0.5 to 4.0 v digital input or output voltage, 5v tolerant normal (2) fail-safe (3) -0.5 to 6.50 -0.5 to 3.80 v v all remaining digital input or output voltage nom. 1.8v nom. 3.3v -0.5 to (vdd+0.5) -0.5 to (vdd3+0.5) v t j operating junction temperature range -40 to 125 c t stg storage temperature -55 to 150 c symbol parameter value unit r th j-amb thermal resistance junction to ambient 68 c/w
TDA7580 4/31 pin connection (top view) 1 vhi 2 vcm 3 vlo 4 inp 5 inn 6 vcmop 7 gndsd 8 gndosc 9 xti 10 xto 11 vddosc 12 vddmtr 13 ckrefp 14 ckrefn 15 agckey 16 gndmtr 48 gnd 47 vdd 46 tst3_lrckr 45 tst2_sckr 44 lrck_lrckt 43 sclk_sckt 42 sdo0 41 vddh 40 gndh 39 tst1_sdi1 38 tst4_sdi0 37 gpio_sdo1 36 testn 35 gnd 34 vdd 33 resetn 64 vddsd 63 vddh 62 gndh 61 vddiso 60 gnd 59 vdd 58 dbout1 57 dbrq1 56 dbin1 55 dbck1 54 vddh 53 gndh 52 dbout0 51 dbrq0 50 dbin0 49 dbck0 32 addr_sd 31 int 30 rds_cs 29 rds_int 28 gndh 27 vddh 26 iqch3 25 iqch2 24 iqch1 23 iqsync 22 vdd 21 gnd 20 scl_sck 19 miso 18 sda_mosi 17 protsel_ss ifadc debug1 osc. tuner dsp/rds i 2 c/spi hs 3 i rds sai debug0 ifadc modulator power supply pins pair oscillator power supply pins pair tuner clock out and agc keying dac power supply pins pair core logic 1.8v power supply pins pair i/o ring 3.3v power supply pins pair
5/31 TDA7580 pin description n name type description notes after reset 1 vhi a internally generated ifadc opamps 2.65v (@vdd=3.3v) reference voltage pin for external filtering it needs external 22 m f and 220nf ceramic capacitors 2 vcm a internally generated common mode 1.65v (@vdd=3.3v) reference voltage pin for external filtering it needs external 22 m f and 220nf ceramic capacitors 3 vlo a internally generated ifadc opamps 0.65v (@vdd=3.3v) reference voltage pin for external filtering it needs external 22 m f and 220nf ceramic capacitors 4 inp a positive if signal input from tuner 2.0vpp @vdd=3.3v 5 inn a negative if signal input from tuner 2.0vpp @vdd=3.3v 6 vcmop a internally generated modulator opamps common mode 2.65v (@vdd=3.3v) reference voltage pin for external filtering it needs external 22 m f and 220nf ceramic capacitors 7 gndsd g ifadc modulator analogue ground clean ground, to be star-connected to voltage regulator ground 8 gndosc g oscillator ground clean ground, to be star-connected to voltage regulator ground 9 xti i high impedance oscillator input (quartz connection) or clock input when in antenna diversity slave mode maximum voltage swing is vdd 10 xto o low impedance oscillator output (quartz connection) 11 vddosc p oscillator power supply 3.3v 12 vddmtr p tuner reference clock and agckeying dac power supply 1.8v 13 ckrefp b tuner reference clock positive output. fm 100khz am eu 18khz with internal pull_up, on at reset output 14 ckrefn b tuner reference clock negative output. fm 100khz am eu 18khz with internal pull_up, on at reset output 15 agckey a dac output for tuner agckeying 1.5kohm 30% output impedance. 1vpp 1% output dynamic range 16 gndmtr g tuner reference clock and agc keying dac ground
TDA7580 6/31 17 protsel_ss b dsp0 gpio for control serial interface (low: spi or high: i 2 c) selection at device bootstrap. in spi protocol mode, after boot procedure, spi slave select, otherwise dsp0 gpio0 dsp0 gpio0 5v tolerant with internal pull_up, on at reset input 18 sda_mosi b control serial interface and rds io: - spi mode: slave data in or master data out for main spi and rds spi data in - i 2 c mode: data for main i 2 c or rds i 2 c 5v tolerant with internal pull_up, on at reset input 19 miso b spi slave data out or master data in for main spi and rds spi data out dsp0 gpio1 5v tolerant with internal pull_up, on at reset input 20 scl_sck b bit clock for control serial interface and rds 5v tolerant with internal pull_up, on at reset input 21 gnd g digital core power ground 22 vdd p digital core power supply 1.8v 23 iqsync b high speed synchronous serial interface (hs 3 i) clock if hs 3 i master mode, else dsp1 gpio or dsp1 debug port clock (dbout1) dsp1 gpio0 5v tolerant with internal pull_up, on at reset input 24 iqch1 b high speed synchronous serial interface (hs 3 i) channel 1 data if hs 3 i master mode, else dsp1 gpio or dsp1 debug port request (dbrq1) dsp1 gpio1 5v tolerant with internal pull_up, on at reset input 25 iqch2 b high speed synchronous serial interface (hs 3 i) channel 2 data if hs 3 i master mode, else dsp1 gpio or dsp1 debug port data in (dbin1) dsp1 gpio2 5v tolerant with internal pull_down, on at reset input 26 iqch3 b high speed synchronous serial interface (hs 3 i) channel 3 data if hs 3 i master mode, else dsp1 gpio or dsp1 debug port data out (dbck1) dsp1 gpio3 5v tolerant with internal pull_down, on at reset input 27 vddh p 3.3v io ring power supply (hs 3 i, i 2 c/ spi, rds, int) 28 gndh g 3.3v io ring power ground (hs 3 i, i 2 c/ spi, rds, int) 29 rds_int b rds interrupt to external main microprocessor in case of traffic information dsp1 gpio4 5v tolerant with internal pull_up, on at reset input n name type description notes after reset pin description (continued)
7/31 TDA7580 30 rds_cs b rds chip select. when resetn rising, if rds_cs 0, the rdss spi is selected; else rdss i 2 c dsp1 gpio5 5v tolerant with internal pull_up, on at reset input 31 int i dsp0 external interrupt 5v tolerantwith internal pull_up, on at reset 32 addr_sd b ifs chip master (low) or slave (high) mode selection, latched in upon resetn release. it selects the lsb of the i 2 c addresses. station detector output dsp0 gpio2 5v tolerantwith internal pull_down, on at reset input 33 resetn i chip hardware reset, active low 5v tolerant with internal pull_up 34 vdd p digital power supply 1.8v 35 gnd g digital power ground 36 testn i test enable pin, active low with internal pull_up 37 gpio_sdo1 b dsp0 gpio for boot selection or audio sai0 output. 5v tolerant dsp0 gpio3 with internal pull_up, on at reset input 38 tst4_sdi0 b audio sai0 data input or test selection pin in test mode 5v tolerant dsp0 gpio5with internal pull_up, on at reset input 39 tst1_sdi1 b dsp0 gpio for boot selection or audio sai1 input. test selection pin in test mode. 5v tolerant dsp0 gpio4with internal pull_up, on at reset input 40 gndh g 3.3v io ring power ground (audio sai, resetn, test pins) 41 vddh p 3.3v io ring power supply (audio sai, resetn, test pins) 42 sdo0 b radio or audio sai0 data output 5v tolerant with internal pull_up, on at reset output 43 sclk_sckt b sai0 receive and transmit bit clock (master or slave with asrc); sai1 transmit bit clock 5v tolerant with internal pull_up, on at reset input 44 lrck_lrckt b sai0 receive and transmit leftright clock (master or slave with asrc); sai1 transmit leftright clock 5v tolerant with internal pull_up, on at reset input n name type description notes after reset pin description (continued)
TDA7580 8/31 45 tst2_sckr b sai0 transmit bit clock; sai1 receive and transmit bit clock. or test selection pin in test mode 5v tolerant dsp0 gpio6 with internal pull_up, on at reset input 46 tst3_lrckr b sai0 transmit leftright clock; sai1 receive and transmit bit clock. or test selection pin in test mode dsp0 gpio7 5v tolerant with internal pull_up, on at reset input 47 vdd p digital core power supply 1.8v 48 gnd g digital core power ground 49 dbck0 b debug port clock of dsp0 (dbck0) dsp0 gpio9 5v tolerant with internal pull_down, on at reset input 50 dbin0 b debug port data input of dsp0 (dbin0) dsp0 gpio11 5v tolerant with internal pull_down, on at reset input 51 dbrq0 b debug port request of dsp0 (dbrq0) dsp0 gpio 5v tolerant with internal pull_up, on at reset input 52 dbout0 b debug port data output of dsp0 (dbout0) dsp0 gpio10 5v tolerant with internal pull_up, on at reset input 53 gndh g 3.3v io ring power ground (debug interface, gpio) 54 vddh p 3.3v io ring power supply (debug interface, gpio) 55 dbck1 b dsp1 debug port clock (dbck1) if hs 3 i master mode, else high speed synchronous serial interface (hs 3 i) channel3 data dsp1 gpio9 5v tolerant with internal pull_down, on at reset input 56 dbin1 b dsp1 gpio or dsp1 debug port data in (dbin1) if hs 3 i master mode, else high speed synchronous serial interface (hs 3 i) channel2 data i dsp1 gpio11 5v tolerant with internal pull_down, on at reset input 57 dbrq1 b dsp1 gpio or dsp1 debug port request (dbrq1) if hs 3 i master mode, else high speed synchronous serial interface (hs 3 i) channel1 data 5v tolerant with internal pull_up, on at reset input n name type description notes after reset pin description (continued)
9/31 TDA7580 58 dbout1 b dsp1 gpio or dsp1 debug port data out (dbout1) if hs 3 i master mode, else high speed synchronous serial interface (hs 3 i) clock dsp1 gpio10 5v tolerant with internal pull_up, on at reset input 59 vdd p digital core power supply 1.8v 60 gnd g digital core power ground 61 vddiso p 3.3v n-isolation biasing supply clean 3.3v supply to be star-connected to voltage regulator 62 gndh g 3.3v io ring power ground (modulator digital section) 63 vddh p 3.3v io ring power supply (modulator digital section) 64 vddsd p 3.3v ifadc modulator analogue power supply clean power supply, to be star-connected to 3.3v voltage regulator n name type description notes after reset pin description (continued) i/o type p: power supply from voltage regulator g: power ground from voltage regulator a: analogue i/o i: digital input o: digital output b: bidirectional i/o i/o definition and status z: high impedance (input) o: logic low output x: undefined output 1: logic high output output pp : push-pull/ od : open-drain
TDA7580 10/31 recommended dc operating conditions note: 1. v ddh , v osc , v ddsd are also indicated in this document as v dd3 . all others as v dd . symbol parameter comment min. typ. max. unit v dd 1.8v power supply voltage core power supply 1.7 1.80 1.9 v v ddh 3.3v power supply voltage (1) io rings power supply (with g ndh ) 3.15 3.30 3.45 v v osc 3.3v power supply voltage (1) oscillator power supply (gnd osc ) 3.15 3.30 3.45 v v ddsd 3.3v power supply voltage (1) if adc power supply (with g ndsd ) 3.15 3.30 3.45 v v mtr 1.8v power supply voltage dac-keying and tuner clock power supply (with gnd mtr ) 1.7 1.80 1.9 v general interface electrical characteristics symbol parameter test condition min. typ. max. unit l ilh low level input current i/os@v dd3 (absolute value) v i = 0v (notes 1, 2) without pull-up-down device 1 m a l ihh high level input current i/os@v dd3 (absolute value) v i = v dd3 (notes 1, 2) without pull-up-down device 1 m a l il low level input current i/os@v dd (absolute value) v i = 0v (notes 1, 3, 4) without pull-up-down device 1 m a l ih high level input current i/os@v dd (absolute value) v i = v dd (notes 1, 3, 4) without pull-up device 1 m a i ipdh pull-down current i/os @ v dd3 v i = v dd3 (note 5) with pull-down device 3.2 6.6 10.0 m a i opuh pull-up current i/os @ v dd3 v i = 0v(note 6) with pull-up device -10.0 -6.6 -3.2 m a i opul pull-up current i/os @ v dd v i = 0v (note 3) with pull-up device -5.4 -3.6 -1.8 m a i aihop analogue pin sunk/drawn current on pin1 and pin 6 v i = v dd3 0.95 1.25 1.55 ma v i = 0v -6.25 -5.0 -3.75 ma i acm analogue pin sunk/drawn current on pin 2 v i = v dd3 1.5 2.0 2.5 ma v i = 0v -2.5 -2.0 -1.5 ma i ail analogue pin sunk/drawn current on pin 3 v i = v dd3 3.75 5.0 6.25 ma v i = 0v -1.55 -1.25 -0.95 ma i ain analogue pin sunk/drawn current on pin 4 and pin 5 v i = v dd3 24 32 40 m a v i = 0v -40 -32 -24 m a i aik analogue pin sunk/drawn current on pin 15 v i = v dd 0.8 1.2 1.6 ma v i = 0v (spec absolute value) 1 m a i oz tri-state output leakage v o = 0v or v dd3 (note 1) without pull up/down device 1 m a
11/31 TDA7580 note: 1. the leakage currents are generally very small, <1na. the value given here, 1 m a, is the maximum that can occur after an electro- static stress on the pin. 2. on pins:17 to 20,23 to 26,29 to 33,36 to 39,42 to 46,49 to 52,55 to 58. 3. on pins: 13 and 14. 4. same check on the analogue pin 15 (phisically without pull-up-down) 5. on pins:25, 26,32,49,50,55,56 6. on pins:17 to 20,23 to 24,29 to 31,33,36 to 39,42 to 46,51, 52,57, 58 low voltage cmos interface dc electrical characteristics note: 1. it is the source/sink current under worst case conditions and reflects the name of the i/o cell according to the drive c apability. high voltage cmos interface dc electrical characteristics note: 1. it is the source/sink current under worst case conditions and reflects the name of the i/o cell according to the drive c apability 2. x=4ma for pins 17 to 20,29,30,32,36 to 39,42 to 46; x=8ma for pins 23 to 26,49 to 52,55 to 58. i ozft 5v tolerant tri-state output leakage (without pull up/down device) v o = 0v or v dd (note 1) 1 m a v o = 5.5v 1 3 m a i latchup i/o latch-up current v < 0v, v > v dd 200 ma v esd electrostatic protection leakage, 1 m a 2000 v symbol parameter test condition min. typ. max. unit v il low level input voltage 1.70v <= vdd <= 1.90v 0.3*v dd3 v v ih high level input voltage 1.70v <= vdd <= 1.90v 0.8*v dd3 v v ol low level output voltage i ol = 4ma (notes 1) 0.15 v v oh high level output voltage i ol = -4ma (notes 1) v dd -0,15 v symbol parameter test condition min. typ. max. unit v il low level input voltage 3.15v <= vdd3 <= 3.45v 0.8 v v ih high level input voltage 3.15v <= vdd3 <= 3.45v 2.0 v v ol low level output voltage i ol = xma (notes 1 and 2) 0.15 v v oh high level output voltage i ol = -xma (notes 1 and 2) v dd3 -0.15 v current consumption symbol parameter test condition min. typ. max. unit i dd current through v dd power supply v dd =1.8v,vdd3=3.3v all digital blocks working 120 200 ma i ddh current through v ddh power supply v dd =1.8v,vdd3=3.3v all i/os working with 5pf load 35ma i sd current through v sd power supply v dd =1.8v,vdd3=3.3v 36 45 54 ma i oscdc current through v osc power supply v dd =1.8v,vdd3=3.3v without quartz 5.5 8 10.5 ma general interface electrical characteristics (continued) symbol parameter test condition min. typ. max. unit
TDA7580 12/31 note: 74.1mhz internal dsp clock, at t amb = 25c. current due to external loads not included. oscillator characteristics notes: 1. the accuracy of this figure only depends on the quartz frequency precision: high stability oscillator quartz characteristics dsp core fm stereo decoder characteristics i oscac current through v osc power supply v dd =1.8v,vdd3=3.3v with quartz in fm mode 11 14 17 ma i mtr current through v mtr power supply v dd =1.8v,vdd3=3.3v 5 ma symbol parameter test condition min. typ. max. unit f oscfm oscillator frequency (xti/xto) v osc @ 3.3v 74.1 mhz f oscam oscillator frequency (xti/xto) v osc @ 3.3v 74.106 mhz parameter name parameter value temperature range -55c +125c adjustment tolerance (@ 25c 3c) +/-20ppm frequency stability (-20c +70c) +/-50ppm aging @ 25c 5ppm/year shunt (static) capacitance (co) <6pf packages (holders) um-1; hc-52u; hc-35; hc-48u; hc-49u; hc-50u; hc-51u mode of oscillation at- 3 rd resonance resistance (esr) <35ohm oscillation frequency (without external load) 3 74108000 hz oscillation frequency (12pf parallel load) target 74.1mhz symbol parameter test condition min. typ. max. unit f dspmax maximum dsp clock frequency at 1.7v core power supply and 125c junction temperature 81.5 mhz symbol parameter test condition min. typ. max. unit a_ch channel separation 50 db thd total harmonic distortion 0.02 % (s+n)/n signal plus noise to noise ratio 80 db current consumption (continued) symbol parameter test condition min. typ. max. unit
13/31 TDA7580 sample rate converter mck = 18.525mhz, f sin /f sout = 0.820445366 symbol parameter test condition min. typ. max. unit thd+n total harmonic distortion + noise 20hz to 20khz, full scale, 16 bit inp. -95 db 20hz to 20khz, full scale, 20 bit inp. -98 db 1 khz full scale, 16 bit inp. -95 db 10 khz full scale, 16 bit inp. -95 db 1 khz full scale, 20 bit inp. -105 db 10 khz full scale, 20 bit inp -98 db dr dynamic range 1 khz -60 db - 16 bit inp.,a-weighted 98 db 1 khz -60 db - 20 bit inp.,a-weighted 120 db ipd interchannel phase deviation 0 degree f c cutoff frequency @ -3 db hz r p pass band ripple from 0 to 20khz -0.01 0.01 db r s stopband attenuation @24.1khz -120 db t g group delay fsout = 44.1 khz 540 m s f ratio sampling frequency in/out ratio fsout = 44.1 khz 0.7 1.05
TDA7580 14/31 power on timing figure 1. power on and boot sequence using i 2 c figure 2. power on and boot sequence using spi vdd3 vdd int resetn addr_sd protsel_ss ifs slave=1 rds_cs gpio_sdo1 ifs master=0 i 2 c/sp i master=0 i 2 c/spi slave=1 tst1_sdi1 boot rds init sw download tuner data data sda_mosi t int t sw t reson t rsu t rhd t tun t dat t seq vdd3 vdd int resetn addr_sd protsel_ss ifs slave=1 rds_cs gpio_sdo1 ifs master=0 i 2 c/sp i master=0 i 2 c/spi slave=1 tst1_sdi1 boot rds init sw download tuner data data sda_mosi t int t sw t reson t rsu t rhd t tun t dat t seq
15/31 TDA7580 timing description value unit t int maximux delay for int signal 1 ms t reson minimum resetn hold time at 0 after the start-up 22 ms t rsu minimum data set-up time 1 m s t rhd minimum data hold time 1 m s t seq minimum wait time after boot 4 ms t sw minimum wait time before downloading the program software 1 m s t tun minimum wait time before downloading the software to the fe 1 m s t dat minimum wait time before using interface protocols 1 m s
TDA7580 16/31 sai interface figure 3. sai timings note t dsp = dsp master clock cycle time = 1/f dsp figure 4. sai protocol when rlrs=0; rrel=0; rckp=1; rdir=0 timing description value unit t dsp internal dsp clock period (typical 1/74.1mhz) 13.495 ns t sckr minimum clock cycle 32*t dsp ns t dt sckr active edge to data out valid 40 ns t lrs lrck setup time 16 ns t lrh lrck hold time 9 ns t sdid sdi setup time 16 ns t sdih sdi hold time 9 ns t sckph minimum sck high time 0.5*t sckr ns t sckpl minimum sck low time 0.5*t sckr ns t sckr t sckpl t dt t sdis t lrs t sckph t lrh t sdih valid lrckr sdi0-1 sckr valid (rckp=0) right left sckr sdi0-1 lrckr lsb(n-1) msb(n) msb-1(n) msb-2(n)
17/31 TDA7580 figure 5. sai protocol when rlrs=1; rrel=0; rckp=1; rdir=1. figure 6. sai protocol when rlrs=0; rrel=0; rckp=0; rdir=0. figure 7. sai protocol when rlrs=0; rrel=1; rckp=1; rdir=0. right left sckr sdi0-1 lrckr msb(n-1) lsb(n) lsb+1(n) lsb+2(n) right left sckr sdi0-1 lrckr lsb(n-1) msb(n) msb-1(n) msb-2(n) right left sckr sdi0-1 lrckr lsb(n-1) msb(n) msb-1(n) msb-2(n)
TDA7580 18/31 spi interface figure 8. spi timings symbol description value unit t dsp internal dsp clock period (typical 1/74.1mhz) 13.495 ns master t sclk minimum clock cycle 12*t dsp ns t dtr minimum sclk edge to mosi valid 40 ns t setup minimum miso setup time 16 ns t hold minimum miso hold time 9 ns t sclkh minimum sck high time 0.5*t sclk ns t sclkl minimum sck low time 0.5*t sclk ns t sssetup minimum ss setup time 40 ns t sshold minimum ss hold time 25 ns slave t sclk minimum clock cycle 12*t dsp ns t dtr minimum sclk edge to mosi valid 40 ns t setup minimum mosi setup time 16 ns t hold minimum mosi hold time 9 ns t sclkh minimum sck high time 0.5*t sclk ns t sclk t sclkl t dtr t sssetup t setup t sclkh t hold t sshold valid miso ss scl valid (cpol=0,cpha=0) mosi
19/31 TDA7580 figure 9. spi clocking scheme t sclkl minimum sck high low 0.5*t sclk ns t sssetup minimum ss setup time 40 ns t sshold minimum ss hold time 20 ns symbol description value unit sck(#20) ss(#17) (cpol=0,cpha=0) (cpol=0,cpha=1) (cpol=1,cpha=0) (cpol=1,cpha=1) sck(#20) sck(#20) sck(#20) msb6543210 miso(#19) mosi(#18)
TDA7580 20/31 inter processor transport interface for antenna diversity figure 10. high speed synchronous serial interface - hs 3 i note t dsp = dsp master clock cycle time = 1/f dsp timing description value unit t dsp internal dsp clock period (typical 1/74.1mhz) t mbcc mbc minimum clock cycle 32*t dsp ns t mbco mbc active edge to master data out valid 4 ns t mbcs mbc active edge to master synch valid 4 ns t sdos slave data out setup time 6 ns master bit clock master data out master synch slave data out m2 m3 s0 s1 s2 s3 256 cycles of 74.1mhz t mbcc t mbco master synch master data out master bit clock slave data out t mbcs t sdos
21/31 TDA7580 i 2 c timing figure 11. dsp and rds i 2 c bus timings. symbol parameter test condition standard mode i 2 c bus fast mode i 2 c bus unit min. max. min. max. f scl scll clock frequency 0 100 0 400 khz t buf bus free between a stop and start condition 4.7 C 1.3 C m s t hd:sta hold time (repeated) start condition. after this period, the first clock pulse is generated 4.0 C 0.6 C m s t low low period of the scl clock 4.7 C 1.3 C m s t high high period of the scl clock 4.0 C 0.6 C m s t su:sta set-up time for a repeated start condition 4.7 C 0.6 C m s t hd:dat data hold time 0 C 0 0.9 m s t r rise time of both sda and scl signals cb in pf C 1000 20+ 0.1c b 300 ns t f fall time of both sda and scl signals cb in pf C 300 20+ 0.1c b 300 ns t su;sto set-up time for stop condition 4 C 0.6 C m s t su:dat data set-up time 250 -- -- 100 ns c b capacitive load for each bus line C 400 C 400 pf
TDA7580 22/31 functional description the TDA7580 ic is a complete solution for high performance fm/am car radio receivers, and has high pro- cessing power to allow audio processing of both internal and external audio source. the processing engine is made of programmable dsp, with separate banks of program and data rams. in ad- dition a number of hardware modules (peripherals) which help in the algorithm implementation of channel equal- ization, and fm/am baseband post-processing. the hw architecture allows to perform dual tuner diversity. in this case two TDA7580 are needed: one device must be configurated as master, generates the clock and controls the main data interfaces. the second device becomes slave and converts the second if path, as well as helps the first chip as co-processor. 24-bit dsp core some capabilities of the dsp are listed below: n single cycle multiply and accumulate with convergent rounding and condition code generation n 24 x 24 to 56-bit mac unit n double precision multiply n scaling and saturation arithmetic n 48-bit or 2 x 24-bit parallel moves n 64 interrupt vector locations n fast or long interrupts possible n programmable interrupt priorities and masking n repeat instruction and zero overhead do loops n hardware stack capable of nesting combinations of 7 do loops or 15 interrupts/subroutines n bit manipulation instructions possible on all registers and memory locations, also jump on bit test n 4 pin serial debug interface n debug access to all internal registers, buses and memory locations n 5 word deep program address history fifo n hardware and software breakpoints for both program and data memory accesses n debug single stepping, instruction injection and disassembly of program memory dsp peripherals n clock generation unit (cgu) n stereo decoder (hwster) n serial audio interface (sai) n tuner agc keying dac (keydac) n programmable i/o interface (i2c/bspi) n asynchronous sample rate converter (asrc) n if band pass sigma delta modulator (ifadc) n digital down converter (ddc) n discriminator (cordic) n rds n tuner diversity hs 3 i
23/31 TDA7580 dsp peripherals the peripherals are mapped in the x-memory space. most of them can be handled by interrupt, with software programmable priority. peripherals running at very high rate have direct access to x and y data bus for very fast movement from or to the core, by mean of single cycle instruction. clock generation unit (cgu) and oscillator this unit is responsible for supplying all necessary clocks and synchronization signals to the whole chip. the control status register of this unit contains information about the current working mode (fm,am,oscillator [master mode] or clock buffer [slave mode]), the tuner clock frequency setting, the general setup of the oscillator. this last function is performed inside the cgu, that establishes -using a self-trimming algorithm- which is the current that can bias the oscillator: this feature let the oscillator be independent from process parameters vari- ation. the values of bias current are stored in the control status register of the cgu: 4 bit for the coarse current steps and 6 bit for the fine current steps. the bits relative to the fine current steps can be anyway corrected (written) by the dsp to perform the sw frequency trimming (+/-80hz per step in fm; +/-250hz in am). it sets up the oscillator which works off a quartz crystal of nominally 74.1mhz, generating very low distortion, thus improving the electro magnetic interference. in fm mode the oscillator generates 74.1mhz, meanwhile in am mode this frequency is shifted to 74.106mhz. the quartz characteristics are defined earlier in this document. in slave mode the oscillator behaves as a buffer: the chip can be then driven using an external clock. the clock divider, placed in this unit, gives the tuner the reference clock (100khz in fm and am us , 18khz in am eu ). stereo decoder (hwster) the fully digital hardware stereo decoder does all the signal processing necessary to demodulate an fm mpx signal which is prepared by the channel equalization algorithm in the digital if sampling device. it makes up of pilot tone dependent mono/stereo switching as well as stereoblend and highcut. selectable deemphasis time constant allow the use of this module for different fm radio receiver standards. there are built-in filters for field strength processing. in order to obtain the maximum flexibility the field strength processing and noise cancellation, however, are implemented as software inside the programming dsp, which has to provide control signals for the stages softmute, stereoblend, and highcut. serial audio interface (sai) the two sai modules have been embedded in such a way great flexibility is available in their use. the two modules are fully separate and they each have a receive and a transmit channel, as well as they can be selected as either master or slave. the bit clocks and left&right clocks are routed through the pins, so the audio interface can be chosen to be adapted to a large variety of application. one sai transmit channel can have the asynchronous sample rate converter in front, thus separate different audio rate domains. additional feature are: n support of 16/24/32 bit word length n programmable left/right clock polarity n programmable rising/falling edge of the bit clock for data valid n programmable data shift direction, msb or lsb received/transmitted first
TDA7580 24/31 i 2 c interfaces the inter integrated circuit bus is a single bidirectional two-wire bus used for efficient inter ic control. all i 2 c bus compatible devices incorporate an on-chip interface which allows them communicate directly with each oth- er via the i 2 c bus. every component hooked up to the i 2 c bus has its own unique address whether it is a cpu, memory or some other complex function chip. each of these chips can act as a receiver and /or transmitter on its functionality. two pins are used to interface both i 2 c of the dsp and rds, which have different internal i 2 c address, thus reducing the on-board pin interconnections. serial peripheral interfaces the dsp and rds can have this serial interface, alternative to the i 2 c one. dsp and rds spi modules have separate pin for chip select. the dsp spi has a ten 24bit-words deep fifo for both receive and transmit sections, which reduces dsp pro- cessing overhead even at high data rate. the serial interface is needed to exchange commands and data over the lan. during an spi transfer, data is transmitted and received simultaneously. a serial clock line synchronizes shifting and sampling of the informa- tion on the two serial data lines. a slave select line allows individual selection of a slave spi device. when an spi transfer occurs an 8-bit word is shifted out one data pin while another 8-bit character is simulta- neously shifted in a second data pin.the central element in the spi system is the shift register and the read data buffer. the system is single buffered in the transfer direction and double buffered in the receive direction. high speed serial synchronous interface (hs 3 i) the high speed serial synchronous interface is a module to send and receive data at high rate (up to 9.25mbit/ s per channel) in order to exchange data between 2 separate TDA7580 chip. the exchanged data are related to signals that are used to increase reception quality in car radio systems, which make use of antenna diversity based upon two separate antenna and tuner sections. the channel synchronization clock has a programmable duty cycle, so to reduce in-band harmonics noise. tuner agc keying dac (keydac) this dac provides the front-end tuner with an analogue signal to be used to control the automatic gain con- trolled stage, thus giving all time the best voltage dynamic range at the ifadc input. asynchronous sample rate converter (asrc) this hardware module provides a very flexible way to adapt the internal audio rate, to the one of an external source. it does not require further work off the dsp. there is no need to explicitly configure the input and the output sample rates, as the asrc solves this problem with an automatic digital ratio locked loop. main features are: n automatic tracking of sample frequency n fully digital ratio locked loop n sampling clock jitter rejection n up-conversion up to 1:2 ratio n linear phase
25/31 TDA7580 if band pass sigma delta analogue to digital converter (ifadc) the ifadc is a band pass sigma delta a to d converter with sampling rate of 37.05mhz (nominal) and notch frequency of 10.7mhz. the structure is a second order switched capacitor multi bit modulator with self calibra- tion algorithm to adjust the notch frequency. the differential ended input allows 4.0vpp voltage dynamic range, and reduces the inferred noise back to the previous stage (tuner), and in turn gives high rejection to common mode noises. the high linearity (very high imd) is needed to fulfill good response of the channel equalization algorithm. low thermal and 1/f noise assures high dynamic range. digital down converter (ddc) the ddc module allows to evaluate the in-phase and quadrature components of the incoming digital if signal. the i and q computation is performed by the ddc block, which at the same time shifts down to 0-if frequency the incoming digital signal. after the down conversion the rate is still very high (at the 37.05mhz rate); a sinck filter samples data down by a factor of 32, decreasing it to 1.1578mhz. an additional decimation is performed by the subsequent fir filters, thus lowering the data rate at the final 289.45khz, being the mpx data rate. rds the rds block is an hardware cell able to process rds/rbds signal, intended for recovering the inaudible rds/rbds information which are transmitted by most of fm radio broadcasting stations. it comprises of the following: n demodulation of the european radio data system (rds) n demodulation of the us radio broadcast data system (rdbs) n automatic group and block synchronisation with flywheel mechanism n error detection and correction n ram buffer with a storage capacity of 24 rds blocks and related status information n i 2 c and spi interface, with pins shared with the dsp i 2 c/spi after filtering the oversampled mpx signal, the rds/rdbs demodulator extracts the rds data clock, rds data signal and the quality information. the following rds/rbds decoder synchronizes the bitwise rds stream to a group and block wise information. this processing also includes error detection and error correction algorithms. in addition, an automatic flywheel control avoids exhausting data exchange between rds/rdbs processor and the host.
TDA7580 26/31 application diagram hereafter are some examples of applications in which the TDA7580 can be used. they are just basic references as the device can operate. figure 12. radio mode with external slave audio dac in this mode an external slave stereo dac, like the st tda7535, can be easily connected and the TDA7580 outputs the audio from radio station at 36khz rate. figure 13. radio mode with external master audio device an external digital audio device is connected externally as a digital audio master, and the internal TDA7580 sample rate converter is responsible for the conversion from internal 36khz to the external audio rate. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 tst3_lrckr 45 tst2_sckr 44 lrck_lrckt 43 sclk_sckt 42 sdo0 41 40 39 tst1_sdi1 38 tst4_sdi0 37 gpio_sdo1 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 8 7 6 5 TDA7580 tda7535 dual dac fs=36khz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 tst3_lrckr 45 tst2_sckr 44 lrck_lrckt 43 sclk_sckt 42 sdo0 41 40 39 tst1_sdi1 38 tst4_sdi0 37 gpio_sdo1 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 TDA7580 external audio receiver fs with its owned audio rate fs
27/31 TDA7580 figure 14. audio mode with external slave audio device the 2 stereo channel serial audio interface of the TDA7580 chip allows a very flexible application in which external audio source/sinks can be connected. the example shows an external cd player digital output giving the main fs audio rate of the whole system. this rate is also the one of the external dacs and an adc, being configured as slave. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 tst3_lrckr 45 tst2_sckr 44 lrck_lrckt 43 sclk_sckt 42 sdo0 41 40 39 tst1_sdi1 38 tst4_sdi0 37 gpio_sdo1 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 8 7 6 5 TDA7580 fs=44.1khz 1 2 3 4 8 7 6 5 tda7535 cd player adc analog in fs=44.1khz
TDA7580 28/31 electrical application scheme the following application diagram must be considered an example. for the real application set-up refers the application notes are necessary .
29/31 TDA7580 package marking
TDA7580 30/31 tqfp64 dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.18 0.23 0.28 0.007 0.009 0.011 c 0.12 0.16 0.20 0.0047 0.0063 0.0079 d 12.00 0.472 d1 10.00 0.394 d3 7.50 0.295 e 0.50 0.0197 e 12.00 0.472 e1 10.00 0.394 e3 7.50 0.295 l 0.40 0.60 0.75 0.0157 0.0236 0.0295 l1 1.00 0.0393 k 0 (min.), 7 (max.) a a2 a1 b c 16 17 32 33 48 49 64 e3 d3 e1 e d1 d e 1 k b tqfp64 l l1 seating plane 0.10mm outline and mechanical data
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics a 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan -malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com 31/31 TDA7580

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